Texas Instruments /MSP432P411V /LCD_F /LCDBMCTL

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Interpret as LCDBMCTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCDBLKMODx_0)LCDBLKMODx 0 (LCDBLKPREx_0)LCDBLKPREx 0 (LCDBLKDIVx_0)LCDBLKDIVx 0 (LCDDISP_0)LCDDISP 0 (LCDCLRM_0)LCDCLRM 0 (LCDCLRBM_0)LCDCLRBM

LCDCLRBM=LCDCLRBM_0, LCDBLKMODx=LCDBLKMODx_0, LCDBLKDIVx=LCDBLKDIVx_0, LCDBLKPREx=LCDBLKPREx_0, LCDCLRM=LCDCLRM_0, LCDDISP=LCDDISP_0

Description

LCD_F blinking and memory control

Fields

LCDBLKMODx

Blinking mode

0 (LCDBLKMODx_0): Blinking disabled

1 (LCDBLKMODx_1): Blinking of individual segments as enabled in blinking memory register LCDBMx.

2 (LCDBLKMODx_2): Blinking of all segments

3 (LCDBLKMODx_3): Switching between display contents as stored in LCDMx and LCDBMx memory registers.

LCDBLKPREx

Clock pre-scaler for blinking frequency

0 (LCDBLKPREx_0): Divide by 512

1 (LCDBLKPREx_1): Divide by 1024

2 (LCDBLKPREx_2): Divide by 2048

3 (LCDBLKPREx_3): Divide by 4096

4 (LCDBLKPREx_4): Divide by 8162

5 (LCDBLKPREx_5): Divide by 16384

6 (LCDBLKPREx_6): Divide by 32768

7 (LCDBLKPREx_7): Divide by 65536

LCDBLKDIVx

Clock divider for blinking frequency

0 (LCDBLKDIVx_0): Divide by 1

1 (LCDBLKDIVx_1): Divide by 2

2 (LCDBLKDIVx_2): Divide by 3

3 (LCDBLKDIVx_3): Divide by 4

4 (LCDBLKDIVx_4): Divide by 5

5 (LCDBLKDIVx_5): Divide by 6

6 (LCDBLKDIVx_6): Divide by 7

7 (LCDBLKDIVx_7): Divide by 8

LCDDISP

Select LCD memory registers for display

0 (LCDDISP_0): Display content of LCD memory registers LCDMx

1 (LCDDISP_1): Display content of LCD blinking memory registers LCDBMx

LCDCLRM

Clear LCD memory

0 (LCDCLRM_0): Contents of LCD memory registers LCDMx remain unchanged

1 (LCDCLRM_1): Clear content of all LCD memory registers LCDMx

LCDCLRBM

Clear LCD blinking memory

0 (LCDCLRBM_0): Contents of blinking memory registers LCDBMx remain unchanged

1 (LCDCLRBM_1): Clear content of all blinking memory registers LCDBMx

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